- Low
- 53,047
- Average
- 69,208
- Median
- 68,000
- High
- 86,577
Engineer, Design Verification Test Salary
50
34
42
Engineer, Design Verification Test average salary is $69,208, median salary is $68,000 with a salary range from $53,047 to $86,577.
Engineer, Design Verification Test salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Design Verification Test salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Engineer, Design Verification Test salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Design Verification Test salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Savannah College Of Art And Design | 53,047-53,047 | Savannah, GA, 31401 | 2018 | Savannah College Of Art And Design Engineer, Design Verification Test Salaries (1) Engineer, Design Verification Test Savannah, GA Salaries |
| Marvell Semiconductor | 86,577-86,577 | Santa Clara, CA, 95050 | 2014 | Marvell Semiconductor Engineer, Design Verification Test Salaries (2) Engineer, Design Verification Test Santa Clara, CA Salaries |
| Marvell Semiconductor | 68,000-68,000 | Santa Clara, CA, 95050 | 2013 | Marvell Semiconductor Engineer, Design Verification Test Salaries (2) Engineer, Design Verification Test Santa Clara, CA Salaries |
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Engineer, Design Verification Test salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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