- Low
- 107,000
- Average
- 109,500
- Median
- -
- High
- 112,000
Engineer, Senior Asic Design Verification Salary
44
69
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Engineer, Senior Asic Design Verification average salary is $109,500, median salary is $- with a salary range from $107,000 to $112,000.
Engineer, Senior Asic Design Verification salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Senior Asic Design Verification salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Engineer, Senior Asic Design Verification salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Senior Asic Design Verification salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Marvell Semiconductor | 112,000-112,000 | Santa Clara, CA, 95050 | 2018 | Marvell Semiconductor Engineer, Senior Asic Design Verification Salaries (2) Engineer, Senior Asic Design Verification Santa Clara, CA Salaries |
| Marvell Semiconductor | 107,000-107,000 | Santa Clara, CA, 95050 | 2015 | Marvell Semiconductor Engineer, Senior Asic Design Verification Salaries (2) Engineer, Senior Asic Design Verification Santa Clara, CA Salaries |
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Engineer, Senior Asic Design Verification salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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