- Low
- 105,400
- Average
- 130,358
- Median
- -
- High
- 155,316
Sr Staff Asic Design/verification Engineer Salary
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71
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Sr Staff Asic Design/verification Engineer average salary is $130,358, median salary is $- with a salary range from $105,400 to $155,316.
Sr Staff Asic Design/verification Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr Staff Asic Design/verification Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Sr Staff Asic Design/verification Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr Staff Asic Design/verification Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Synaptics | 155,316-155,316 | San Jose, CA, 95101 | 2018 | Synaptics Sr Staff Asic Design/verification Engineer Salaries (1) Sr Staff Asic Design/verification Engineer San Jose, CA Salaries |
| Marvell Semiconductor | 105,400-105,400 | Santa Clara, CA, 95050 | 2014 | Marvell Semiconductor Sr Staff Asic Design/verification Engineer Salaries (1) Sr Staff Asic Design/verification Engineer Santa Clara, CA Salaries |
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Sr Staff Asic Design/verification Engineer salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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