- Low
- 70,990
- Average
- 84,173
- Median
- 86,300
- High
- 93,100
Sr. Verification Design Engineer Salary
64
92
64
Sr. Verification Design Engineer average salary is $84,173, median salary is $86,300 with a salary range from $70,990 to $93,100.
Sr. Verification Design Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr. Verification Design Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Sr. Verification Design Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr. Verification Design Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Genesys Telecommunications Laboratories | 70,990-70,990 | Daly City, CA, 94014 | 2017 | Genesys Telecommunications Laboratories Sr. Verification Design Engineer Salaries (1) Sr. Verification Design Engineer Daly City, CA Salaries |
| Marvell Semiconductor | 93,100-93,100 | Santa Clara, CA, 95050 | 2013 | Marvell Semiconductor Sr. Verification Design Engineer Salaries (3) Sr. Verification Design Engineer Santa Clara, CA Salaries |
| Marvell Semiconductor | 86,300-86,300 | Santa Clara, CA, 95050 | 2012 | Marvell Semiconductor Sr. Verification Design Engineer Salaries (3) Sr. Verification Design Engineer Santa Clara, CA Salaries |
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Sr. Verification Design Engineer salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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专利代理人/10K+上不封顶/双休包住工资专利分析师助理工资知识产权专员/双休高薪工资 Sr. Verification Design Eng... Jobs
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